Varactor with improved tuning range

ABSTRACT

A varactor has a plurality of alternating P− wells and N+ regions formed in a silicon layer. Each of the P− wells forms a first N+/P− junction with the N+ region on one of its side and a second N+/P− junction with the N+ region on the other of its sides. A gate oxide is provided over each of the P− wells, and a gate silicon is provided over each of the gate oxides. The potential across the gate silicons and the N+ regions controls the capacitance of the varactor.

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates to a varactor that has a greater C_(max)/C_(min) ratio so that its tuning range is improved.

BACKGROUND OF THE INVENTION

[0002] Modulators, voltage controlled oscillators, and other devices employing varactors have been previously proposed for use in RF applications. A varactor is a device whose capacitance varies with the voltage thereacross. One of the criteria that dictates the design of a varactor for RF applications, particularly for RF wireless applications, is the capacitive switching ratio R. The capacitive switching ratio R is defined as C_(max)/C_(min), where C_(max) is the maximum capacitance of the varactor, and where C_(min) is the minimum capacitance of the varactor.

[0003]FIG. 1 is a graph showing the capacitance response of a typical varactor, where capacitance is given along the y-axis and voltage is given along the x-axis. As can be see by the graph of FIG. 1, the capacitive switching ratio of a typical varactor is on the order of 2 to 2.5.

[0004] Such a low capacitive switching ratio has limited both the tuning range and the quality factor Q of known varactors. However, higher capacitive switching ratios have been difficult to attain, particularly in RF wireless applications where power consumption is of necessity kept as low as possible.

[0005] The present invention is directed to a varactor that is arranged to attain a higher capacitance switching ratio R than that described above.

SUMMARY OF THE INVENTION

[0006] In accordance with one aspect of the present invention, a varactor comprises a silicon layer, a P− well in the silicon layer, first and second N+ regions in the silicon layer, a gate oxide above the P− well, and a silicon gate above the gate oxide. The first N+ region forms a first N+/P− junction with the P− well, and the second N+ region forms a second N+/P− junction with the P− well.

[0007] In accordance with another aspect of the present invention, a varactor comprises a silicon layer, a plurality of alternating P− wells and N+ regions in the silicon layer, a gate oxide above each of the P− wells, and a silicon gate above each of the gate oxides. Each P− well forms a first N+/P− junction with the N+ region on one side of the P− well and a second N+/P− junction with the N+ region on the other side of the P− well.

[0008] In accordance with yet another aspect of the present invention, a method comprises the following: forming a plurality of alternating P− wells and N+ regions in a silicon layer such that each P− well forms a first N+/P− junction with the N+ region on one side and a second N+/P− junction with the N+ region on the other side; forming a plurality of gate oxides, wherein each of the gate oxides is formed above a corresponding one of the P− wells; forming a plurality of silicon gates, wherein each of the silicon gates is formed above a corresponding one of the gate oxides; electrically coupling each of the silicon gates together; and, electrically coupling each of the N+ regions together.

[0009] In accordance with a further aspect of the present invention, a varactor is formed by a MOS transistor structure and has a capacitive switching ratio equal to or greater than 5.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] These and other features and advantages will become more apparent from a detailed consideration of the invention when taken in conjunction with the drawings in which:

[0011]FIG. 1 is a graph showing the capacitance response of a typical varactor;

[0012]FIG. 2 is a top view of a varactor according to one embodiment of the present invention;

[0013]FIG. 3 is a cross-sectional view of a portion of the varactor shown in FIG. 2;

[0014]FIG. 4 is a graph showing the capacitance response of a varactor according to one construction of the present invention;

[0015]FIG. 5 is a graph showing the capacitance response of a varactor according to another construction of the present invention; and,

[0016]FIG. 6 is an equivalent circuit diagram for the varactor shown in FIGS. 2 and 3.

DETAILED DESCRIPTION

[0017] As shown in FIGS. 2 and 3, a varactor 10 is formed on a silicon-on-insulation (SOI) structure 12 having a silicon layer 14 formed over an insulation layer 16. The insulation layer 16 may be formed of an oxide such as SiO₂ and, as shown in FIG. 2, is formed over a handle wafer 18. Silicon having a high resistivity may be used for the handle wafer 18. A plurality of MOS transistors is used to construct the varactor 10. A cross-sectional side view of one such transistor 20 is shown in FIG. 3.

[0018] As shown in FIG. 3, the silicon layer 14 is doped to form two N+ regions 22 and 24, one of which forms a source and the other of which forms a drain of the transistor 20. The silicon in the silicon layer 14 between the N+ regions 22 and 24 is suitably doped in order to form a P− well 26. A gate oxide 28 is provided over the P− well 26, and a polysilicon gate 30 is provided over the gate oxide 28. The gate oxide 28 and the polysilicon gate 30 are defined by suitable dielectric spacers 32 and 34.

[0019] As shown in FIG. 2, the varactor 10 includes a plurality of transistors each of which may be similar to the transistor 20. Thus, the varactor 10 has a plurality of gates 36. In accordance with the varactor 10 as shown in FIG. 3, each of the gates 36 is polysilicon formed over a gate oxide, and each of the gates 36 extends over a corresponding P− well that is also formed in the silicon layer 14. N+ regions 38 are formed in the silicon layer 14 on each side of each of the gates 36. Accordingly, the P− wells and the N+ regions 38 alternate in the silicon layer 14.

[0020] A first metal layer 40 is electrically coupled to each of the gates 36. Similarly, a second metal layer 42 is electrically coupled to each of the N+ regions 38. The varactor 10, whose equivalent circuit is shown in FIG. 6, is coupled across a pair of electrical lines 44 and 46.

[0021] As can be seen from FIGS. 2 and 3, the gates 36 are silicon islands fully isolated from the SOI structure 12 by corresponding gate oxides. The P− wells and the N+ regions of each of the transistors making up the varactor 10 extend completely through the silicon layer 14 from the top of the silicon layer 14 to the insulation layer 16. Moreover, the varactor 10 has no P+ to P− direct body contact, and the varactor 10 is formed by using a series of connecting node pairs, where each node pair includes a gate and an N+ region.

[0022] The capacitance of the varactor 10 varies according to the voltage applied across the first and second metal layers 40 and 42. As this voltage increases, the varactor 10 moves from the depletion mode to the inversion mode. During this operation, the potential on the body of the transistor (i.e., the P− wells) is allowed to float with respect to the gates and the source and drain regions.

[0023]FIG. 4 is a graph showing the capacitance response of the varactor 10, where capacitance is given along the y-axis and the voltage drop applied across the first and second metal layers 40 and 42 is given along the x-axis. The varactor 10 covered by the graph of FIG. 4 has twelve polysilicon gates, where each polysilicon gate has a width W of 110 microns and a length L of 6.8 microns. As can be see by the graph of FIG. 4, the capacitive switching ratio of the varactor 10 in this case is on the order of 33.

[0024]FIG. 5 is a graph showing the capacitance response of another construction of the varactor 10. The varactor 10 covered by the graph of FIG. 5 has six polysilicon gates, where each polysilicon gate has a width W of 110 microns and a length L of 1.2 microns. As can be see by the graph of FIG. 5, the capacitive switching ratio of the varactor 10 in this case is on the order of 5.

[0025] Certain modifications of the present invention have been discussed above. Other modifications will occur to those practicing in the art of the present invention. For example, as described above, the varactor 10 is formed on an SOI structure. Instead, the varactor 10 may be formed on bulk silicon or SOS (silicon-on-sapphire).

[0026] Accordingly, the description of the present invention is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and the exclusive use of all modifications which are within the scope of the appended claims is reserved. 

We claim:
 1. A varactor comprising: a silicon layer; a P− well in the silicon layer; first and second N+ regions in the silicon layer, wherein the first N+ region forms a first N+/P− junction with the P− well, and wherein the second N+ region forms a second N+/P− junction with the P− well; a gate oxide above the P− well; and, a silicon gate above the gate oxide.
 2. The varactor of claim 1 wherein the silicon gate comprises a polysilicon gate.
 3. The varactor of claim 1 wherein the silicon layer is formed over an insulation layer so that the silicon layer and the insulation layer together form an SOI structure.
 4. The varactor of claim 3 wherein the insulation layer is formed over a layer of high resistivity silicon.
 5. The varactor of claim 1 wherein the silicon layer is formed from bulk silicon.
 6. The varactor of claim 1 wherein the silicon layer is formed over a sapphire layer so that the silicon layer and the sapphire layer together form an SOS structure.
 7. The varactor of claim 1 wherein the P− well forms a transistor body, and wherein the transistor body is allowed to float.
 8. The varactor of claim 1 wherein the gate silicon has a width to length ratio of approximately 16 to
 1. 9. The varactor of claim 1 further comprising a first metallization coupled to the gate silicon and a second metallization coupled to the N+ regions.
 10. The varactor of claim 1 wherein the first and second N+/P− junctions extend from a top surface to a bottom surface of the silicon layer.
 11. A varactor comprising: silicon layer; a plurality of alternating P− wells and N+ regions in the silicon layer, wherein each P− well forms a first N+/P− junction with the N+ region on one side of the P− well and a second N+/P− junction with the N+ region on the other side of the P− well; a gate oxide above each of the P− wells; and, a silicon gate above each of the gate oxides.
 12. The varactor of claim 11 wherein the silicon gate above each of the gate oxides comprises a polysilicon gate above each of the gate oxides.
 13. The varactor of claim 11 wherein the silicon layer is formed over an insulation layer so that the silicon layer and the insulation layer together form an SOI structure.
 14. The varactor of claim 13 wherein the insulation layer is formed over a layer of high resistivity silicon.
 15. The varactor of claim 11 wherein the silicon layer is formed from bulk silicon.
 16. The varactor of claim 11 wherein the silicon layer is formed over a sapphire layer so that the silicon layer and the sapphire layer together form an SOS structure.
 17. The varactor of claim 11 wherein the P− wells form a transistor body, and wherein the transistor body is allowed to float.
 18. The varactor of claim 11 wherein each of the gate silicons has a width to length ratio of approximately 16 to
 1. 19. The varactor of claim 11 further comprising a first metallization coupled to the silicon gate above each of the gate oxides and a second metallization coupled to each of the N+ regions.
 20. The varactor of claim 11 wherein each of the N+/P− junctions extends from a top surface to a bottom surface of the silicon layer.
 21. A method comprising: forming a plurality of alternating P− wells and N+ regions in a silicon layer such that each P− well forms a first N+/P− junction with the N+ region on one side and a second N+/P− junction with the N+ region on the other side; forming a plurality of gate oxides, wherein each of the gate oxides is formed above a corresponding one of the P− wells; forming a plurality of silicon gates, wherein each of the silicon gates is formed above a corresponding one of the gate oxides; electrically coupling each of the silicon gates together; and, electrically coupling each of the N+ regions together.
 22. The method of claim 21 wherein each of the silicon gates comprises a polysilicon gate.
 23. The method of claim 21 further comprising forming the silicon layer over an insulation layer so that the silicon layer and the insulation layer together form an SOI structure.
 24. The method of claim 23 further comprising forming the insulation layer over a layer of high resistivity silicon.
 25. The method of claim 21 wherein the silicon layer comprises a bulk silicon layer.
 26. The method of claim 21 further comprising forming the silicon layer over a sapphire layer so that the silicon layer and the sapphire layer together form an SOS structure.
 27. The method of claim 21 wherein the P− wells form a transistor body, and wherein the transistor body is allowed to float.
 28. The method of claim 21 wherein each of the silicon gates is formed so as to have a width to length ratio of approximately 16 to
 1. 29. The method of claim 21 wherein each of the N+/P− junctions extends from a top surface to a bottom surface of the silicon layer.
 30. A varactor formed by a MOS transistor structure and having a capacitive switching ratio equal to or greater than
 5. 